1. Field of the Disclosure
Generally, the present disclosure is related to sophisticated integrated circuits, and more particularly, to integrated circuits wherein dummy gate structures are provided and methods for forming the same.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, in particular field effect transistors. In a field effect transistor, a gate structure including a gate electrode and a gate insulation layer that provides electrical insulation between the gate electrode and the channel region may be provided. Adjacent the channel region, a source region and a drain region that are doped differently than the channel region may be provided. Depending on an electric voltage applied to the gate electrode, the field effect transistor can be switched between an ON-state and an OFF-state, wherein an electrical conductivity of the channel region in the ON-state is substantially greater than an electrical conductivity of the channel region in the OFF-state.
Integrated circuits including field effect transistors may be formed in accordance with semiconductor-on-insulator (SOI) technology. In SOI technology, active regions including source, channel and drain regions of the transistors are formed in a relatively thin semiconductor layer that is separated from a support substrate, which may be a semiconductor substrate, by an electrically insulating layer. SOI technology may have some advantages associated therewith, which include a reduced power consumption of an SOI integrated circuit compared to a bulk semiconductor integrated circuit having the same performance. A further improvement of the performance of an integrated circuit may be obtained by fully depleted SOI (FDSOI) technology, wherein the semiconductor layer has a relatively small thickness so that a full depletion of the channel regions of the field effect transistors can be obtained.
For reducing leakage currents of field effect transistors while maintaining a relatively high capacity between the gate electrode and the channel region, gate insulation layers including high-k materials such as, for example, hafnium dioxide, may be used, which may be combined with gate electrodes including metals having a workfunction that matches the type of the field effect transistors (P-channel or N-channel, respectively). For providing an electrical isolation between adjacent field effect transistors, shallow trench isolation (STI) structures may be employed. Shallow trench isolation structures may be formed by forming trenches extending through the semiconductor layer and the electrically insulating layer into the support substrate of the SOI structure. The trenches may be filled with an electrically insulating material such as, for example, silicon dioxide. When shallow trench isolation structures are formed in accordance with known techniques, a non-planar topography of the surface of the electrically insulating material in the trenches may be obtained.
In some examples of integrated circuits, dummy gate structures may be formed over shallow trench isolation structures. The dummy gate structures may have a configuration corresponding to the configuration of gate structures that are provided in field effect transistors. In particular, each of the dummy gate structures may include a dummy gate insulation layer that includes a high-k dielectric material and a workfunction adjustment metal layer. Providing dummy gate structures over shallow trench isolation structures may help to provide a relatively uniform spacing between adjacent ones of the gate structures and the dummy gate structures in the integrated circuit. This may have some advantages when the gate structures and dummy gate structures are formed by means of patterning processes including photolithography, such as, for example, an improved dimensional accuracy.
However, forming dummy gate structures over shallow trench isolation structures as described above may have some issues associated therewith, which may be related to the topography of the surfaces of the shallow trench isolation structures. The topography of the shallow trench isolation structures may cause difficulties in the patterning of the dummy gate structures. Furthermore, the topography of the shallow trench isolation structures may increase a likelihood of high-k or metal gate footing occurring, wherein residues of high-k dielectric materials that are employed for the formation of the dummy gate insulation layers or metals used for the formation of the workfunction adjustment metal layers remain on portions of the shallow trench isolation structures adjacent the dummy gate structures. Moreover, forming dummy gate structures over shallow trench isolation structures may be associated with limitations of the pitch between adjacent gate and dummy gate structures.
In view of the situation described above, the present disclosure provides integrated circuits and methods for forming the same that may help to substantially avoid or at least reduce some or all of the above-mentioned issues.